The present invention relates in general to data sampling circuits used in the field of data communication, and more specifically to a sampling data output circuit capable of flexibly accommodating frequency variations.
With wireless data communication systems, a signal transmitted over a radio frequency is down-converted to baseband frequency, which is subjected to signal processing, such as sampling, to produce a desired signal. Wireless systems of this type typically include a synchronous system and an asynchronous system. Synchronous systems, which use a preamble synchronization signal to ensure synchronization on the transmitting and receiving ends for phase alignment, suffer a problem in that the period until synchronization is attained (training period) can be very long depending on use, thus resulting in cost disadvantages. On the other hand, asynchronous systems allow for phase adjustment without use of a preamble synchronization signal.
FIG. 1 shows a schematic block diagram of a sampling data output circuit (100) used in such an asynchronous system. The circuit (100) comprises an oversampling portion (104) that receives an input signal (102) and samples it at an oversampling frequency (CLK4×) that is four times the sampling frequency. The oversampling portion (104) comprises four delay elements (106). An output of each of the delay elements (106) is connected, respectively, to first through fourth phase output portions (112–118) and further connected to an error detector (not shown).
FIG. 2 shows a timing chart for explaining the operation of the system (100) shown in FIG. 1. The input signal (102) is first sampled at the oversampling portion (104) and is sequentially stored in the delay elements in alignment with the oversampling clock (CLK4×). The outputs of the delay elements (106) are fed to input portions (110) of the first through fourth phase output portions (112–118), and output from each of the phase output portions in alignment with a sampling clock (CLK). These output signals are signal series that are out of phase from each other, and correspond to versions of the input signal (102) sampled at phase timings as denoted by p1, p2, p3, and p4. After error checking by the error detector (not shown), a desired signal series is selected. Such a system presumes that the sampling clock (CLK) and the oversampling clock (CLK4×), which is a multiplied version thereof, are the same on the transmitting and receiving ends.
However, the frequencies on the transmitting and receiving ends are not necessarily the same due to factors, such as communication apparatus manufacturing variability, changes over time, variations in temperature, and other environmental influences. If the clock or frequency is offset, a problem as described below may occur. For example, if the frequency on the receiving end is higher by 0.5% than that on the transmitting end, the data sampling point is offset by 0.5 samples per 100 samples (100*0.005=0.5 samples), or by one whole sample per 200 samples (see FIG. 2). Thus, if the data length of the packets transmitted is about 100 samples, an offset in the sampling point is 0.5 samples at most; thus, error-free data may be determined by selecting either of the four phase candidates. However, if the packet length is 200 samples or longer, the sampling point is completely offset by one or more samples, so that an error will result even when either of the phase candidates is selected. By reducing the packet length, for example, about 100 samples long in this case, the problem associated with frequency offset may be addressed theoretically. However, the data length to be transmitted is typically very long. Thus, there is a problem in that, with a shorter packet length, the processing required to reconstruct the original long data is complicated.
The present invention solves at least one of the aforedescribed problems.